PETsys TOFPET2 ASIC

PETsys Time-of-Flight PET ASIC

The PETsys High Performance TOFPET2 ASIC is a new 64 channel chip for the readout and digitization of signals from fast photon detectors in applications where a high data rate and fast timing is required. It uses a low threshold for timing and a high threshold for accepting the event. Both thresholds are separately configurable for each channel. Every time one of the 64 channels exceeds the high threshold a record is created giving the channel number, the time and the charge of the event. Activity in one channel does not cause any dead-time on the other channels.

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TOFPET2 a high-performance ASIC for time and amplitude measurements of SiPM signals in time-of-flight applications

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PETsys TOF ASIC E. Kit
Figure 1
Detail of test board showing the TOFPET2 ASIC bonded on the board before the application of a protective epoxy layer. Standard it is provided as BGA package.
PETsys TOFPET2 ASIC
Figure 2
Pulse hight spectrum obtained with a radioactive source of 22Na and with a LYSO crystal of 3x3x5 mm3 mounted on a KETED-PM3325-WB SiPM at 4 V overvoltage and at 20° C. The charge signal is integrated in a time window of 350ns. The energy resolution at 511 keV is 10.5% after corretions for the SiPM non-linearity.
FEM128 Module
Figure 3
Time difference between the two signals from a positron annihilation event. Measured at 15°C with a 22Na point source and two 2x2x3 mm3 LYSO:Ce crystals coupled to two Hamamatsu S13361-3050AE MPPC arrays.

Main Features

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Designed in standard CMOS 110 nm technology.

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Signal amplification and discrimination for each of 64 independent channels.

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Dual branch analogue interpolation TDCs for each channel. The first branch is used for timing measurement. The second branch can either be used for time-over-threshold (ToT) or charge measurement (ADC).

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Quad-bufered charge integration for each TDC or ADC in each channel

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Dynamic range: 1500 pC.

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SNR 25 dB for Qin=200 fC (about one p. e.) and input capacitance of 320 pF.

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TDC time binning: 30 ps.

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Gain adjustment per channel: 1, 1/2, 1/4, 1/8.

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On-chip calibration pulse generator with 6-bit programmable amplitude.

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Max channel hit rate: 600 kHz.

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Rejects dark counts without triggering, allowing to handle over 1 MHz of dark counts.

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Separately configurable thresholds for each channel.

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Configurable charge integration time up to two microseconds.

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Fully digital output, 4 LVDS data links double data rate (DDR) compatible.

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Max output data rate: 3.2 Gb/s.

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Clock frequency: 200 MHz.

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Power consumption per channel: 8.2 mW, depending on certain settings